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Exploring Cache Coherence Protocols: Snooping vs Directory-Based

Updated on Mar 28,2024

Exploring Cache Coherence Protocols: Snooping vs Directory-Based

Table of Contents

  1. Cache Coherence Protocols: An Introduction
  2. Types of Cache Coherence Protocols
    • 2.1 Snooping Protocols
      • 2.1.1 Write-Invalidate Protocols
      • 2.1.2 Write-Update Protocols
    • 2.2 Directory-Based Protocols
  3. Snooping Protocols: A Closer Look
    • 3.1 Write-Invalidate Protocols Explained
    • 3.2 Write-Invalidate Protocol Example
    • 3.3 Comparing Write-Invalidate and Write-Update Protocols
  4. The MSI Protocol: An Example of Write-Invalidate Protocol
  5. Conclusion
  6. Resources

Cache Coherence Protocols: An Introduction

In multi-core systems, cache coherence protocols are used to maintain coherence in shared memory multiprocessor systems. These protocols ensure that multiple cores or processors accessing the same memory location see the most up-to-date value. There are different classes of cache coherence protocols, including snooping protocols and directory-based protocols. In this lesson, we will focus on snooping protocols, specifically write-invalidate protocols.

Types of Cache Coherence Protocols

Snooping Protocols

Snooping protocols are a type of cache coherence protocol where the cache controllers monitor the bus for broadcasts of addresses. If a cache controller detects that it has a copy of a cache block whose address is being broadcasted, it reacts in a certain way. Snooping protocols require the address of the block being read or written to be broadcasted to all cores, making them suitable for systems with a bus. These protocols are commonly used in relatively small systems with a limited number of cores.

Write-Invalidate Protocols

Write-invalidate protocols are a type of snooping protocol. When a core performs a write operation on a memory block, all other copies of the block in other caches are invalidated. This means that the other caches can no longer use their copies of the block and must fetch the updated value from memory or the cache that performed the write. Write-invalidate protocols ensure that the most recent value is always retrieved from memory. However, they Consume less bus bandwidth compared to write-update protocols.

Write-Update Protocols

Write-update protocols, also a type of snooping protocol, differ from write-invalidate protocols in that they do not invalidate all other copies of a memory block when a write operation occurs. Instead, they update all copies of the block in each cache. This means that every cache containing a copy of the block must be updated with the new value. Write-update protocols consume more bus bandwidth compared to write-invalidate protocols.

Directory-Based Protocols

Directory-based protocols are another class of cache coherence protocols. In these protocols, the sharing status of a memory block, indicating which caches have a copy of it, is stored in a central location called the directory. Directory-based protocols are more scalable than snooping protocols and are therefore commonly used in larger shared memory systems.

Snooping Protocols: A Closer Look

Write-Invalidate Protocols Explained

Write-invalidate protocols operate by invalidating all other copies of a memory block when a write operation occurs. This ensures that only one cache holds the most up-to-date value of the memory block. When a core performs a write operation, it writes the new value into its cache and sends a Broadcast to all other caches, indicating that their copies are no longer valid. This way, any subsequent read operations will fetch the most recent value from the cache that performed the write or directly from memory.

Write-Invalidate Protocol Example

Let's consider an example to understand how write-invalidate protocols work. Initially, the contents of memory location X are set to 0. Core A reads the value of X and fetches a copy of it in its private cache. Then, Core B also reads the value of X and fetches its own copy. When Core A writes a new value of 1 to X, it updates its cache with the new value and invalidates the copy of X in Core B's cache. Finally, when Core B reads X again, it retrieves the value from Core A's cache, which contains the most recent value.

Comparing Write-Invalidate and Write-Update Protocols

When a processor repeatedly writes the same WORD, write-invalidate protocols only require one invalidation, while write-update protocols require multiple updates or broadcasts to all caches. Similarly, when a processor writes different words within the same cache block, write-invalidate protocols again require only one invalidation, while write-update protocols require multiple broadcasts. However, write-invalidate protocols introduce a delay between writing data in one core and reading the new data in another core, as it first requires an invalidation and then fetching the new data. Write-invalidate protocols consume less bus bandwidth compared to write-update protocols.

The MSI Protocol: An Example of Write-Invalidate Protocol

One specific example of a write-invalidate protocol is the MSI (Modified, Shared, Invalid) protocol. In this protocol, a cache block can be in one of three states: modified, shared, or invalid. When a core writes to a memory block, it enters the modified state, invalidating all other copies. When a core reads a memory block and it is in the modified state, it must first write the modified data back to memory before sharing it with other caches. If a cache block is in the shared state, it means that multiple caches have a valid copy of the block. The MSI protocol efficiently maintains cache coherence in multi-core systems.

Conclusion

Cache coherence protocols play a crucial role in maintaining the consistency of shared memory in multi-core systems. Snooping protocols, such as write-invalidate protocols, are commonly used in smaller systems, whereas directory-based protocols are more suitable for larger systems. Write-invalidate protocols invalidate all other copies of a memory block when a write occurs, while write-update protocols update all copies. The choice between these protocols depends on factors like bus bandwidth and the frequency of write operations. The MSI protocol is an example of a write-invalidate protocol that efficiently ensures cache coherence.

Resources

Ultimate High-Performance PC Build: Powerful Components Revealed!
Avoid Common Mistakes: Proper Motherboard Installation Guide

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