Mastering PCI Express Design with Intel FPGAs

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Table of Contents

1. Introduction
2. Requirements for Using the Heart IP
3. Placing Transceiver Channels
4. Clocking Rules for Transceiver Channels
5. Setting Up I/O Locations for Transceiver Channels
6. Assigning I/O Standards to Pins
7. Configuring Transceivers for Specific Protocols
8. Built-in PLLs for Clocking
9. Configuration Via Protocol (CVP)
10. Debugging Link Training Issues
11. Debugging BIOS Enumeration Issues
12. Conclusion

📚 Introduction

Welcome to the presentation on designing with Intel Stratix 10 Intel, Aria 10, and Intel Cyclone 10 GX FPGA Heart IP for PCI Express. In this online training, we will be exploring the rules and techniques for properly using the Heart IP in your FPGA designs. By the end of this training, you will have a clear understanding of the requirements, configuration techniques, and debugging strategies related to the Heart IP.

📚 Requirements for Using the Heart IP

Before we dive into the details of using the Heart IP, it's important to understand the requirements associated with it. The Heart IP is specifically designed for use with the Intel Stratix 10, Intel Aria 10, and Intel Cyclone 10 GX FPGAs. It serves as the interface between the FPGA and the PCI Express link, providing the necessary functionality for data transmission.

To ensure proper operation, the Heart IP has specific rules that must be followed. These rules govern the placement of transceiver channels, the bonding of channels for multi-channel operation, and the restrictions on where individual channels can be placed within the device. By adhering to these rules, you can avoid board-level issues and ensure the reliable operation of your PCI Express link.

📚 Placing Transceiver Channels

One of the key considerations when using the Heart IP is the placement of transceiver channels. Transceiver channels provide the physical layer of the PCI Express link, and their proper placement is crucial for optimal operation.

Within the Intel Stratix 10, Intel Aria 10, and Intel Cyclone 10 GX devices, transceiver channels are organized into groups of six. Each group of channels is associated with a specific transceiver bank, and the Heart IP is connected to one or more dedicated transceiver banks.

When placing transceiver channels, it is important to ensure that the channels are assigned to the appropriate transceiver location. This involves assigning the serial input (RX) and output (TX) pins to I/O locations on the device using tools like the Interface Planner and Pin Planner. Additionally, the appropriate I/O standards must be applied to these pins to ensure compatibility with the PCI Express protocol.

📚 Clocking Rules for Transceiver Channels

Clocking is another important aspect of using the Heart IP. Proper clocking ensures the synchronization of data transmission and reception over the PCI Express link. For the Intel Stratix 10, Intel Aria 10, and Intel Cyclone 10 GX devices, there are specific clocking rules that must be followed.

The devices include built-in phase-locked loops (PLLs) dedicated to transceiver operation. These PLLs support different data rates and multiplication values, depending on the specific requirements of your design. The type of PLL used depends on the desired data rate and the generation of PCI Express operation (Gen 1, Gen 2, or Gen 3).

For Gen 1 and Gen 2 operation, the fractional PLLs (FPLLs) are used. These PLLs support data rates up to 12.5 gigabits per Second and offer a wide range of multiplication values. On the other HAND, Gen 3 operation requires the use of both the FPLLs and the high performance PLLs (ATX PLLs). The ATX PLLs support the maximum transceiver data rates of the device and produce less output jitter at higher frequencies.

When setting up clocking for the Heart IP, it is important to select the appropriate PLL based on the desired data rate and generation of operation. This can be done through the Intel Quartus Prime Pro software, which provides tools for configuring and managing the PLLs.

📚 Setting Up I/O Locations for Transceiver Channels

After defining the transceiver channels and their clocking parameters, the next step is to assign the appropriate I/O locations to these channels. This involves specifying the physical locations on the device where the transceiver channels will be connected.

In the Intel Quartus Prime Pro software, tools like the Interface Planner and Pin Planner can be used for this purpose. These tools allow you to assign the serial input (RX) and output (TX) pins to specific I/O locations on the device.

Proper placement of the transceiver channels is crucial for ensuring the reliable operation of the PCI Express link. It is important to carefully follow the guidelines provided by Intel to ensure that the channels are placed in the correct locations. Failure to do so may result in performance issues or other problems with the link.

📚 Assigning I/O Standards to Pins

Once the transceiver channels have been placed and their I/O locations assigned, the next step is to assign the appropriate I/O standards to the pins. This ensures that the signals transmitted and received by the transceivers are compatible with the PCI Express protocol.

The Intel Quartus Prime Pro software provides options for assigning I/O standards to the pins. The I/O standards define the voltage levels and signaling characteristics of the signals transmitted and received by the transceivers.

For the serial inputs (RX) and outputs (TX), the High-Speed Differential I/O (HSDIO) standard is typically used. This standard is specifically designed for high-speed serial interfaces like PCI Express. For the transmit output buffers, the High-Speed Current Steering Logic (HCSL) standard is used. This standard provides the necessary drive strength and termination characteristics for PCI Express transmission.

It is important to carefully select and apply the appropriate I/O standards to the pins to ensure reliable operation of the transceivers and compatibility with the PCI Express protocol.

📚 Configuring Transceivers for Specific Protocols

In addition to the PCI Express protocol, the transceivers in the Intel Stratix 10, Intel Aria 10, and Intel Cyclone 10 GX devices can support other protocols and interfaces. To configure the transceivers for a specific protocol, you need to set up the appropriate parameters and settings.

The Intel Quartus Prime Pro software provides tools for configuring the transceivers. These tools allow you to specify the protocol-specific settings, such as the data rate, encoding scheme, and link width. By configuring the transceivers correctly, you can ensure that they operate reliably and efficiently for your specific application.

It is important to consult the documentation and guidelines provided by Intel for each specific protocol or interface you intend to use with the transceivers. This will ensure that you configure the transceivers correctly and avoid any compatibility or performance issues.

📚 Built-in PLLs for Clocking

Clocking is a critical aspect of using the Heart IP, and the Intel Stratix 10, Intel Aria 10, and Intel Cyclone 10 GX devices include built-in phase-locked loops (PLLs) dedicated for transceiver operation.

The devices offer different types of PLLs, depending on the desired data rate and generation of PCI Express operation. For Gen 1 and Gen 2 operation, the fractional PLLs (FPLLs) are used. These PLLs support a wide range of multiplication values and provide the necessary clocking for the transceivers.

For Gen 3 operation, in addition to the FPLLs, the devices also utilize the high-performance PLLs (ATX PLLs). These PLLs support the maximum transceiver data rates and produce less output jitter at higher frequencies.

By using the appropriate PLLs and configuring them correctly, you can ensure the proper clocking of the transceivers and the reliable operation of the PCI Express link.

📚 Configuration Via Protocol (CVP)

Configuration Via Protocol (CVP) is a powerful feature available in the Intel Stratix 10, Intel Aria 10, and Intel Cyclone 10 GX devices. CVP allows you to configure the FPGA through the Heart IP using the PCI Express link, providing flexibility, security, and control over the configuration process.

With CVP, you can easily configure the periphery and Heart IP blocks within the FPGA without the need for external programming devices. This allows you to quickly and easily update the FPGA configuration, even during runtime.

To use CVP, you need to enable the "Enable Configuration Via Protocol" option in the Heart IP Parameter Editor. This will activate the autonomous feature of the Heart IP, allowing it to come out of reset and configure the FPGA after power-up. The Intel Quartus Prime Pro software provides the necessary tools for generating the configuration files required for CVP.

By utilizing CVP, you can reduce the complexity of your design, minimize the required flash memory for configuration storage, and enhance the security and control over the FPGA configuration process.

📚 Debugging Link Training Issues

Link training is a critical step in establishing a reliable PCI Express link. During link training, the transceivers detect each other's presence and negotiate the best settings for data transmission.

In some cases, link training may encounter issues or failures. To debug link training issues, it is important to have visibility into the LTSSM (Link Training and Status State Machine) progression. The Signal Tap Logic Analyzer, a tool provided by Intel Quartus Prime Pro, allows you to capture and analyze the LTSSM states, helping you identify the root cause of the problem.

Additionally, third-party PCI Express protocol analyzers can be used to capture and analyze the packets as they travel across the PCI Express link. These analyzers can decode the packet information, correlate split transactions, and detect any packet errors. This can be especially helpful in diagnosing complex link training issues.

By using these debugging tools and following the guidelines and recommendations provided by Intel, you can effectively debug and resolve link training issues, ensuring the successful establishment of a reliable PCI Express link.

📚 Debugging BIOS Enumeration Issues

After link training, another important step is the BIOS enumeration, where the operating system detects and configures the PCI Express devices in the system. In some cases, the Heart IP may not be recognized during the enumeration process, leading to communication issues between the FPGA and the host system.

To debug BIOS enumeration issues, you can try performing a soft reset to force the enumeration process again while allowing the FPGA to retain its configuration. This may help in situations where the FPGA was still being configured during the initial enumeration.

Alternatively, you can use CVP to program the FPGA, ensuring that the FPGA and the Heart IP are fully configured and ready before the enumeration process begins. By using CVP, you can guarantee that the Heart IP is enumerated and recognized by the host system.

By following proper debugging techniques and considering the recommendations from Intel, you can overcome BIOS enumeration issues and ensure the proper functioning of the PCI Express link.

📚 Conclusion

In this online training, we have covered the key aspects of designing with the Intel Stratix 10, Intel Aria 10, and Intel Cyclone 10 GX FPGA Heart IP for PCI Express. We have explored the requirements, placement rules, clocking considerations, configuration techniques, and debugging strategies associated with the Heart IP.

By following the guidelines and recommendations provided by Intel, you can successfully implement the Heart IP in your FPGA designs and establish a reliable and efficient PCI Express link. The Intel Quartus Prime Pro software, along with various debugging tools, provides the necessary resources for designing and debugging the Heart IP.

If you need further assistance or additional resources, Intel provides a range of self-help resources, including web pages, community forums, and training courses dedicated to FPGA technologies.

Thank you for your time, and we hope this training has been informative and helpful in your FPGA design journey.

Highlights

• Understanding the requirements for using the Heart IP in Intel FPGAs
• Placing transceiver channels and assigning I/O locations
• Applying clocking rules and using built-in PLLs for reliable operation
• Configuring transceivers for specific protocols and interfaces
• Exploring the benefits and techniques of Configuration Via Protocol
• Debugging link training issues with the Signal Tap Logic Analyzer
• Troubleshooting BIOS enumeration issues for proper system recognition

FAQs

Q: Can I use the Heart IP with other FPGA families? A: No, the Heart IP is specifically designed for use with the Intel Stratix 10, Intel Aria 10, and Intel Cyclone 10 GX FPGAs.

Q: Is Configuration Via Protocol supported in all FPGA configurations? A: No, Configuration Via Protocol is supported only in endpoint configurations of the Heart IP. It is not supported in root port or other configurations.

Q: What tools can I use to debug link training issues? A: The Signal Tap Logic Analyzer, as well as third-party PCI Express protocol analyzers, can be used to debug link training issues by capturing and analyzing LTSSM states and packet information.

Q: How can I ensure proper clocking of the transceivers? A: By selecting the appropriate PLLs and configuring them correctly using the Intel Quartus Prime Pro software, you can ensure proper clocking of the transceivers.

Q: What should I do if the Heart IP is not recognized during BIOS enumeration? A: You can try performing a soft reset to force the enumeration process again, or use Configuration Via Protocol to ensure that the Heart IP is fully configured before enumeration begins.

Resources

• Intel FPGA Landing Pages
• Intel FPGA Community Forum
• Intel FPGA Training Courses
• Intel Quartus Prime Pro Software Documentation