Boot NEOS 2 on Max 10 FPGAs with On-Chip RAM and Flash

Boot NEOS 2 on Max 10 FPGAs with On-Chip RAM and Flash

Table of Contents:

1. Introduction
2. Background on Max 10 FPGAs 2.1. CFM - Configuration Flash Memory 2.2. UFM - User Flash Memory
3. Booting NEOS 2 from Altera On-Chip RAM 3.1. Configuring the Altera On-Chip RAM IP 3.2. Configuring the NEOS 2 IP 3.3. Compiling and Programming the Max 10 FPGA
4. NEOS 2 Application Execution from Altera On-Chip Flash 4.1. Configuring the Altera On-Chip Flash IP 4.2. Configuring the NEOS 2 Gen2 4.3. Compiling and Programming the Max 10 FPGA
5. NEOS 2 Dual Boot Configuration Flow
6. Conclusion
7. Resources

Introduction In this article, we will explore the various ways to boot NEOS 2 on Max 10 FPGAs from Altera. We will discuss the different memory regions in Max 10 FPGAs and how they are utilized for booting NEOS 2. Additionally, we will guide you through the steps of configuring the necessary IPs and programming the FPGA for NEOS 2 booting. So, let's dive in and discover the exciting world of NEOS 2 booting on Max 10 FPGAs!

Background on Max 10 FPGAs Max 10 FPGAs, developed by Altera, revolutionize the concept of nonvolatile integration with advanced processing capabilities in a low-cost, single-chip, small form factor programmable logic device. These FPGAs consist of two built-in memory regions: the Configuration Flash Memory (CFM) and the User Flash Memory (UFM). The size of these flash memories varies depending on the selected device. The NEOS 2 software image, in the form of a soft file, is stored inside the CFM, while the NEOS 2 software image in the form of a hex file is stored in the UFM region. These soft and hex files are combined into a single programming file (PO file) to be programmed into the Max 10 FPGAs.

Booting NEOS 2 from Altera On-Chip RAM Booting NEOS 2 from Altera On-Chip RAM is a supported method for all device families, including Max 10 FPGAs. By initializing the Altera On-Chip RAM with the NEOS 2 application hex image, the need for a boot copier is eliminated, as the hex file image becomes part of the programming file (PFF) itself. To begin, we need to configure the Altera On-Chip RAM IP, which will store the NEOS hex image size. We choose a suitable memory size, such as 32 kilobytes, for our application. Once the memory is initialized, the NEOS hex image will be included in the soft image during compilation. After configuring the NEOS 2 IP and generating the HDL file, we proceed to build the NEOS 2 software image. The software project is based on a template, such as Hollow World, and the software image is generated by converting the Al file into a hex file. Finally, the soft file is converted into a PO file and programmed into the Max 10 FPGAs using the Quartus software.

NEOS 2 Application Execution from Altera On-Chip Flash Another configuration method for booting NEOS 2 is to execute the application directly from the Altera On-Chip Flash memory. This solution is suitable for Max 10 NEOS 2 applications that run with limited on-chip RAM resources. By utilizing the Altera Load function, the writable section is copied to the on-chip RAM, while the read-only section remains in the Altera On-Chip Flash memory. This minimizes the RAM usage. To configure this, we need to set up the NEOS 2 Gen2, the Altera On-Chip Flash IP, and the On-Chip Memory IP. The NEOS 2 Gen2 is configured to point the reset vector to the Altera On-Chip Flash and the exception vector to the Altera On-Chip RAM. After generating the Quartus archive, we ensure that the Quartus configuration mode matches the configuration mode of the Altera On-Chip Flash IP. The software project is updated to allocate the dynamic memory space required by the application. Finally, the PO file is generated by combining the soft and hex files, and the Max 10 FPGA is programmed.

NEOS 2 Dual Boot Configuration Flow In the NEOS 2 dual boot configuration flow, we discuss the process of booting NEOS 2 from both Altera On-Chip Flash and Altera On-Chip RAM. This configuration allows for flexibility in choosing the boot method depending on the application requirements. It involves configuring the necessary IPs, setting the reset and exception vectors, and programming the Max 10 FPGA accordingly.

Conclusion Booting NEOS 2 on Max 10 FPGAs is a powerful capability that enhances the functionality of these devices. With different booting methods, such as booting from Altera On-Chip RAM or Altera On-Chip Flash, developers have the flexibility to choose the most suitable approach for their applications. By following the steps outlined in this article, you can successfully configure and program your Max 10 FPGA for NEOS 2 booting. So, start exploring the endless possibilities with NEOS 2 on Max 10 FPGAs today!

Resources

• Max 10 Altera On-Chip Flash User Guide: [link]
• Altera NEOS 2 Documentation: [link]

Highlights:

• Boot NEOS 2 on Max 10 FPGAs using Altera On-Chip RAM or On-Chip Flash
• Configuring the Altera IPs and generating the necessary files for programming
• NEOS 2 dual boot configuration flow for flexible booting options
• Enhancing the functionality of Max 10 FPGAs with NEOS 2

FAQ:

Q: What are the memory regions in Max 10 FPGAs? A: Max 10 FPGAs consist of two built-in memory regions: the Configuration Flash Memory (CFM) and the User Flash Memory (UFM).

Q: Can NEOS 2 boot from Altera On-Chip RAM? A: Yes, NEOS 2 can be booted from Altera On-Chip RAM, eliminating the need for a boot copier.

Q: Is it possible to execute NEOS 2 applications directly from Altera On-Chip Flash? A: Yes, by utilizing the Altera Load function, NEOS 2 applications can be executed directly from Altera On-Chip Flash.

Q: Can Max 10 FPGAs support dual boot configuration for NEOS 2? A: Yes, Max 10 FPGAs can be configured for dual boot, allowing the flexibility of booting from both Altera On-Chip RAM and Altera On-Chip Flash.