Booting NEOS 2 on Max 10 FPGAs: Methods and Techniques

Table of Contents

1. Introduction
2. Booting NEOS 2.0 from Max 10 FPGAs
3. Overview of Max 10 FPGAs
4. Understanding the Memory Regions
5. Booting NEOS 2 Application from Altera On-Chip RAM
6. Configuring Altera On-Chip RAM
7. Initializing the Memories
8. Configuring the NEOS 2 IP
9. Generating the HDL and Software Image
10. Programming the Max 10 FPGA with NEOS 2
11. Executing NEOS 2 Application from Altera On-Chip Flash
12. Configuring the On-Chip Flash and Memory
13. Generating the NEOS 2 Software Image
14. Combining the Soft and Hex Files
15. Programming the Max 10 FPGA with NEOS 2
16. Conclusion

Introduction

In this article, we will explore the different ways to boot NEOS 2.0 from Altera's Max 10 FPGAs. Max 10 FPGAs are revolutionary nonvolatile integration devices with advanced processing capabilities, all packed into a low-cost single chip. We will delve into the various methods to configure and initialize the required memory regions, and then proceed to discuss the two main approaches for booting NEOS 2 applications: using Altera On-Chip RAM and executing from Altera On-Chip Flash. By the end of this article, you will have a thorough understanding of the process and be able to successfully boot NEOS 2.0 on your Max 10 FPGAs.

Booting NEOS 2.0 from Max 10 FPGAs

Max 10 FPGAs come equipped with built-in memory regions known as Configuration Flash Memory (CFM) and User Flash Memory (UFM). The CFM stores the FPGA's configuration, while the UFM is used for user data storage. The size of these flash memories varies depending on the specific Max 10 device selected. In order to boot NEOS 2.0, we need to load the software image (hex file) into the UFM region and the NEOS 2 application (soft file) into the CFM. These two files are combined into a single programming file (PO file) that can be used to program the Max 10 FPGA.

Overview of Max 10 FPGAs

Max 10 FPGAs are designed to bring advanced processing capabilities to a wide range of applications. These FPGAs offer a combination of features that make them highly desirable for cost-sensitive projects. Some key features of Max 10 FPGAs include:

• Nonvolatile integration: Max 10 FPGAs feature nonvolatile flash memory, which means that the configuration data is retained even after power is removed. This eliminates the need for external configuration devices and simplifies the design process.

• Low-cost solution: Max 10 FPGAs are designed with cost in mind, making them a cost-effective choice for many applications. The integration of various components onto a single chip helps reduce the overall system cost, making it an attractive option for budget-conscious projects.

• Small form factor: Max 10 FPGAs come in a compact form factor, allowing for easy integration into space-constrained designs. This makes them suitable for applications where size and weight are critical factors.

• Programmable logic: Max 10 FPGAs offer a high degree of programmability, allowing for flexibility in implementing complex logic functions. This makes them suitable for a wide range of applications, from simple control systems to complex signal processing algorithms.

Understanding the capabilities and features of Max 10 FPGAs is essential when working with NEOS 2.0 and booting applications from these FPGAs.

Understanding the Memory Regions

Max 10 FPGAs consist of two built-in memory regions: CFM (Configuration Flash Memory) and UFM (User Flash Memory). The CFM is used to store the FPGA's configuration, while the UFM is available for storing user data. The size of these flash memories varies depending on the specific Max 10 device selected.

During the boot process, the NEOS 2 application (soft file) is stored in the CFM, while the software image (hex file) is stored in the UFM. These two files are combined into a single programming file (PO file) that can be used to program the Max 10 FPGA.

To boot NEOS 2.0 from a Max 10 FPGA, it is crucial to understand the memory regions and how they are utilized. This understanding will help us configure and initialize the memories correctly for a successful boot process.

Booting NEOS 2 Application from Altera On-Chip RAM

One of the supported methods for booting NEOS 2 applications from Max 10 FPGAs is by executing the application from the Altera On-Chip RAM. This method eliminates the need for an external boot copier, as the NEOS hex image becomes part of the programming file itself.

To boot NEOS 2 from the Altera On-Chip RAM, we need to configure the Altera On-Chip RAM IP and initialize its memory content. The NEOS hex image will be included in the soft image during compilation. In the Vector tab of the NEOS 2 IP configuration, we need to choose the reset vector and exception vector and point them to the On-Chip RAM.

After configuring the IP and generating the HDL, we can proceed to build the NEOS 2 software image. Our NEOS 2 software project is based on the template "Hello World." Upon building the software image, an Al file is generated, which needs to be converted to a hex file.

Converting the Al file to a hex file is a straightforward process. Simply right-click on the project file, go to "Make Target," choose "Build," and select "M init generate." Click on "Build" again to generate the hex file. This hex file will be used to program the Max 10 FPGA.

By following these steps, we can successfully boot NEOS 2 applications from Altera On-Chip RAM. This method provides a convenient way to execute NEOS 2 applications without the need for external booting devices.

Pros:

• Eliminates the need for an external boot copier
• NEOS hex image becomes part of the programming file

Cons:

• Requires proper configuration and initialization of On-Chip RAM

Stay tuned for Part Two of this article, where we will explore another method of booting NEOS 2 from Max 10 FPGAs and discuss the dual boot configuration flow.