Enabling External FPGA Boot on Arria 10 SoC: A Step-by-Step Guide

Table of Contents

• Introduction
• Requirements and Preparation for External FPGA Boot
• Configuration on U-Boot and Hardway
• testing and Success of External FPGA Boot
• What is External FPGA Boot?
• Differences Between External FPGA Boot and Boot from Flash
• Items Needed for External FPGA Boot
• Configuration for Supporting External FPGA Boot
• Hardware Configuration
• Integrating the Intel Hex into FPGA SRAM Object File

Introduction

In this article, we will explore the topic of enabling booting from an AR10 FPGA and how to configure it for supporting external FPGA boot. We will start by understanding what external FPGA boot is and then list out the requirements and preparation needed for it. Next, we will discuss the configuration process on both U-Boot and Hardway on the AR10 development board. Finally, we will cover the testing of the system and the steps to achieve a successful external FPGA boot.

🔍 What is External FPGA Boot?

External FPGA boot refers to the execution of the boot process directly from FPGA memory, such as the FPGA on-chip RAM (FPGA RAM). This is different from booting from flash, where the boot source binary is stored in flash memory and loaded into the HPS memory before execution. In external FPGA boot, the boot source binary and the FPGA RAM object file can be programmed through a PC host and then executed from the FPGA memory.

🔍 Differences Between External FPGA Boot and Boot from Flash

The main difference between external FPGA boot and boot from flash lies in the boot source and memory used for execution. In external FPGA boot, the boot source binary is a part of the FPGA RAM object file, while in boot from flash, the binary is stored in flash memory. External FPGA boot allows for direct execution from FPGA memory, eliminating the need to load the binary into HPS memory.

🔍 Items Needed for External FPGA Boot

To enable external FPGA boot, the following items are required:

1. Intel Arria 10 SoC Development Kit
2. Host PC with a serial terminal software (e.g., Minicom for Linux, TeraTerm for Windows)
3. Intel SoC EDS (Embedded Design Suite) and Intel Quartus Prime Pro version 17.0 software installed
4. AR10 GSRD (Golden System Reference Design) installation files

Now that we have an overview of the topic, let's proceed with the detailed steps for configuring and enabling external FPGA boot.

Requirements and Preparation for External FPGA Boot

To support external FPGA boot, certain requirements and preparations need to be fulfilled. Here's what you need to do:

1. Opening the Embedded Command Shell: The first step is to open the embedded command shell. You can find the shell from the path below:

   /path/to/embedded/command/shell

2. Open BSP Editor: Enter the PSP Editor command into the shell to open the BSP Editor.

3. Create New HPS BSP: In the BSP Editor, create a new HPS BSP workspace file. Go to the "File" menu and point to the software HAND off directory as shown in the path below:

   /path/to/software/handoff/directory

4. Select External FPGA Configuration: Edit the BSP by selecting the external FPGA configuration and choosing "Put from SDC" from the drop-down list. This configuration includes the SDMMC driver and allows the use of the pre-built u-boot source, which will be set as the external FPGA configuration.

5. Generate BSP: Click on "Generate" and then exit BSP Editor once the generation is complete.

Configuration on U-Boot and Hardway

Once the software configuration is done, we need to proceed with the configuration on U-Boot and Hardway for supporting external FPGA boot. Follow the steps below:

1. Copy Device Tree Source Files: Chain the file named device3.dts, which is generated by BSP Editor, to socfpga_arria10.dts. Then, copy the DTS source into the drivers/soc/altera/socfpga/arria10 directory.

2. Navigate to the Yu Sources Directory: Navigate to the Yu sources directory where you extracted the sources from the SoC EDS installation.

3. Set Cross Compiler and Clean Sources: Set the cross compiler to ARM and run the command make Mproper to keep the sources in a clean, original stage.

4. Enable External FPGA Boot: Enable external FPGA boot by running the command make SOCFPGA_FJUNCORE_JARVIS_CONFIG=y.

5. Rebuild Sources: Rebuild the sources by running the command make.

6. Combine Binary and DTS Block: Once the U-Boot (UT) is finished building, combine the output binary and the device tree source (DTS) block by running the command mkpimage -d -a armv7 -o utimage -C none -T 2 -B 0x00008000 -E 0x000080ff --data

7. Convert to Intel Hex Format: Finally, convert the combined binary into Intel hex format using the command objcopy -I binary -O ihex utimage utimage.hex.

Testing and Success of External FPGA Boot

To test the external FPGA boot and ensure its success, follow these steps:

1. Connect the Board: Power on the board and connect a UART terminal to the board's UART interface.

2. Connect to the Host PC: Connect the board to the host PC using the JTAG cable and ensure that the PC recognizes the board.

3. Program the Soft: Program the output file created by Quartus using the Quartus programmer.

4. Trigger Warm Reset: Once the programming is complete, trigger a warm reset by pressing the warm reset button on the board.

5. Verify Successful Boot: After the reset, the HPS should execute the external FPGA boot process successfully.

Congratulations! You have successfully enabled external FPGA boot on the AR10 FPGA.

FAQs

Q: What is the difference between external FPGA boot and boot from flash? A: External FPGA boot executes the boot process directly from FPGA memory, while boot from flash loads the boot source binary into HPS memory before executing.

Q: What are the items needed for external FPGA boot? A: To enable external FPGA boot, you will need the Intel Arria 10 SoC Development Kit, a host PC with a serial terminal software, Intel SoC EDS, and Intel Quartus Prime Pro version 17.0 software.

Q: How can I test the success of the external FPGA boot? A: To test the success of external FPGA boot, you need to connect the board, program the soft, and trigger a warm reset. The HPS should then execute the external FPGA boot process successfully.