Optimizing Boot Time and Eliminating SMI Handlers: Exploring PRM

Table of Contents

1. Introduction
2. Understanding the Boot Flow
   • 2.1 Silicon Initiation Package
   • 2.2 UPI Topology Discovery and Routing
   • 2.3 Memory Initialization and ECC
   • 2.4 Address Mapping
   • 2.5 Initialization Process and MP Initiation
   • 2.6 Platform Initialization
   • 2.7 PCI Enumeration and Resource Allocation
   • 2.8 OS Interface and ACPI Tables
   • 2.9 Option ROM and Boot Device Selection
3. Challenges with SMI Handlers
   • 3.1 Complexity and Performance Jitters
   • 3.2 Security Risks and Attack Vectors
4. Proposal: Platform Runtime Mechanism (PRM)
   • 4.1 Introduction to PRM
   • 4.2 Benefits of PRM
   • 4.3 PRM Implementation for ASL Code
   • 4.4 PRM Implementation for Flash and Variables
   • 4.5 PRM Implementation for Hardware SMI
   • 4.6 PRM Implementation for Uncorrectable Errors
5. Alternative Solutions for SMI Handlers
   • 5.1 In-Band Error Handling with BMC
   • 5.2 Machine Check Containment with Error Pins
6. Conclusion
7. Resources

Understanding Boot Time Optimization and Eliminating SMI Handlers

Introduction

Boot time optimization is a critical aspect of system performance, especially in cloud environments where efficiency is paramount. One major challenge in optimizing the boot flow is the usage of System Management Interrupts (SMI) handlers. SMI handlers allow the BIOS to take control of the system at random times, which can lead to unpredictable performance jitters and increased complexity. Moreover, the privileged nature of SMI handlers also poses security risks, making it essential to find alternative solutions. In this article, we will explore the boot flow, discuss the challenges with SMI handlers, and propose the use of the Platform Runtime Mechanism (PRM) as an alternative to eliminate or reduce reliance on SMI handlers.

Understanding the Boot Flow

To optimize boot time and reduce reliance on SMI handlers, it is essential to first understand the boot flow and the different stages involved. The boot flow can be broadly categorized into several key steps:

2.1 Silicon Initiation Package

The boot process begins with the initiation of the silicon package, which involves CPU initialization, loading microcode patches, and setting up empty caches.

2.2 UPI Topology Discovery and Routing

Next, the boot sequence performs UPI (Ultra Path Interconnect) topology discovery and routing. This step is crucial in multi-socket systems, as it ensures the discovery of sockets and determines the least distance route between them, avoiding deadlocks.

2.3 Memory Initialization and ECC

Once UPI topology is established, the boot flow proceeds to memory initialization. This step involves training the DDR (Double Data Rate) memory and initializing the ECC (Error Correcting Code) to ensure data integrity.

2.4 Address Mapping

After memory initialization, the boot process involves address mapping, where the address space is distributed across the sockets in a multi-socket system. This step ensures efficient utilization of memory resources.

2.5 Initialization Process and MP Initiation

The initialization process continues with the start-up of the platform package, where the system's BSP (Boot Strap Processor) is determined. The other cores are then initiated, and initialization commands are issued to set up timers, PCIe configurations, and other platform-specific settings.

2.6 Platform Initialization

During platform initialization, the system interfaces with the operating system, publishing ACPI (Advanced Configuration and Power Interface) tables, BIOS tables, and initiating the BDS (Boot Device Selection) process. This phase sets the foundation for launching the operating system.

2.7 PCI Enumeration and Resource Allocation

Following platform initialization, the boot flow proceeds to PCI enumeration and resource allocation. This standard mechanism involves bus walkthroughs, discovering I/O ranges, and programming bar registers.

2.8 OS Interface and ACPI Tables

The boot process interfaces with the operating system, providing ACPI tables and ASL (ACPI Source Language) code to describe the system's PCI tree hierarchy. These tables enable the OS to interact with the hardware and facilitate proper system management.

2.9 Option ROM and Boot Device Selection

Lastly, the boot flow involves the execution of Option ROM code, which is responsible for initializing various hardware components and performing boot device selection. The BDS face provides multiple choices for launching the desired payload, such as a deluxe boot or customized variations.

Challenges with SMI Handlers

SMI handlers pose several challenges in terms of complexity, performance, and security. Here are some key issues associated with reliance on SMI handlers:

3.1 Complexity and Performance Jitters

The random and frequent invocation of SMI handlers during system operation can lead to increased complexity and performance jitters. With the growth of multi-core systems, SMI handlers become a bottleneck, causing unpredictable stalls and delays. The race conditions and out-of-sync scenarios that arise from multiple Threads invoking SMIs further exacerbate the problem.

3.2 Security Risks and Attack Vectors

SMI handlers, being a powerful mode of system control, open up potential security risks. If an attacker can exploit SMI handlers through a rop or a job chain, it becomes an attractive attack surface. Additionally, the unfettered access to hardware resources in SMM makes it a compelling target for malicious actors.

Proposal: Platform Runtime Mechanism (PRM)

To eliminate or reduce reliance on SMI handlers, we propose the use of the Platform Runtime Mechanism (PRM) as an alternative. PRM serves as a mechanism for ASL code to interface with runtime protocols, providing similar capabilities as SMI handlers without entering the SMM mode. Here's a breakdown of how PRM can be implemented for various tasks:

4.1 Introduction to PRM

PRM is a mechanism that ties API code to runtime protocols, allowing ASL code to call into C code without entering the SMM mode. It leverages existing mechanisms such as ACPI device objects and runtime services to achieve this functionality.

4.2 Benefits of PRM

PRM offers several benefits compared to traditional SMI handlers. It provides transparency, allowing the voice (operating system) to read and audit the code. PRM also offers containment and security, as it operates at the same privilege level as ASL code and cannot modify other system resources directly. Unlike SMI handlers, PRM does not stall all cores during execution, leading to improved performance and reduced complexity.

4.3 PRM Implementation for ASL Code

For ASL code, PRM can be implemented through a bridge driver that binds to ACPI device objects. By notifying the bridge driver from ASL code, it can then call the appropriate C code defined in the runtime protocol. This mechanism allows ASL code to invoke runtime services without entering SMI.

4.4 PRM Implementation for Flash and Variables

In the case of flash updates and variable handling, PRM can be leveraged to avoid SMI handlers. For flash updates, authenticated and non-authenticated variables can be used to determine the level of access required. Non-authenticated variables can be accessed directly without SMI, while authenticated variables can be staged in memory for later update during reboot. This approach ensures secure and efficient flash updates.

4.5 PRM Implementation for Hardware SMI

For hardware-related SMI handlers, PRM provides a mechanism to read hardware status through ASL code and pass the information to C code. This approach eliminates the need for SMM, as ASL code can handle hardware-related tasks without stalling the system.

4.6 PRM Implementation for Uncorrectable Errors

Uncorrectable errors, such as memory errors, can be handled using PRM by utilizing error pins. These error pins can be configured to trigger an ACI interrupt, allowing the support engine, such as the BMC, to read the error information without interrupting the regular flow of SMI handling.

Alternative Solutions for SMI Handlers

While PRM offers an efficient way to eliminate or reduce SMI handlers, there are alternative solutions that can be explored:

5.1 In-Band Error Handling with BMC

In certain cases, it might be preferable to utilize the BMC for error handling instead of relying on SMI handlers. By configuring error pins to generate interrupts, the BMC can Collect error information and perform necessary actions without interrupting the regular flow of the operating system.

5.2 Machine Check Containment with Error Pins

Another alternative solution involves utilizing error pins to trigger machine checks instead of SMI. This approach provides containment for uncorrectable errors, allowing the system to handle errors within the operating system without entering SMM.

Conclusion

Optimizing boot time and reducing reliance on SMI handlers is crucial for improving system performance and security. The proposed use of the Platform Runtime Mechanism (PRM) offers a viable alternative to handle ASL code execution and access runtime protocols without entering SMM. By eliminating or reducing the usage of SMI handlers, system complexity, performance jitters, and security risks can be significantly mitigated. The PRM approach, along with alternative solutions such as BMC-based error handling and machine check containment, provides a more efficient and secure boot flow.

Resources:

• Link 1
• Link 2