Unlocking the Power of OFS: Agilex FPGA Workload Development

Table of Contents

1. Introduction
2. Overview of FPGAs and OFS
3. Traditional FPGA Development Flow
4. OFS and its Benefits
5. Architecture of OFS for Workload Development
6. Choosing Between RTO and API Based Design Flow
7. Building Static or PR Enabled Designs
8. Tools and Features of OFS for Workload Development
9. Development Flow for Building an AFU using OFS
10. Evaluating OFS and testing Software and Hardware

Introduction

In this article, we will explore the use of the Open FPGA Stack (OFS) framework as a starting point for designing workloads based on Agilex FPGAs. We will begin by providing a brief overview of FPGAs and OFS, followed by a discussion on how OFS can reduce development time and enable quick workload development. We'll also dive into the architecture of OFS and highlight the benefits it offers. Furthermore, we'll explore the different design flows and options available when using OFS for workload development. We'll conclude with a step-by-step guide on the development flow for building an AFU (Accelerator Function Unit) using OFS. So, let's get started and unlock the power of OFS for your FPGA-based workload designs.

Overview of FPGAs and OFS

FPGAs provide developers and engineers with the ability to program and execute multiple tasks or instructions in Parallel. These programmable devices allow for flexibility, as new functions and features can be reprogrammed to meet customer changes and updates. Intel offers a range of FPGA products that cater to various size, performance, and power requirements.

The Open FPGA Stack (OFS) is a software and hardware infrastructure that simplifies the development of custom FPGA-based platforms or workloads using Intel design boards. OFS provides reference designs, automated build scripts, and Upstream Linux drivers for native OS support. It also offers user-space tools, software development kits, and open-source source code accessible through GitHub.

Traditional FPGA Development Flow

Before diving into the specifics of OFS, it's essential to understand the traditional FPGA development flow. FPGA development involves both hardware and software aspects. After defining requirements for your design, such as power, performance, and interfaces, significant time is devoted to hardware and software development. This includes stitching together the initial design, iteration, compilation, verification, and achieving optimal routing, timing, and performance. On the software side, additional tasks like developing drivers, patching drivers, and managing the software stack are performed.

The traditional FPGA development flow can take anywhere from 9 to 12 months. However, with OFS, developers are provided with a Timely optimized reference design and a full software stack, significantly reducing time to market. Now, let's dive deeper into OFS and explore its architecture and benefits.

OFS and its Benefits

The Open FPGA Stack (OFS) offers a wide range of benefits for developers and users of Intel FPGAs. It simplifies the development process by providing pre-built reference designs, automated build scripts, and upstream Linux drivers for native OS support. OFS also offers user-space tools and a software development kit for further software customization.

One of the significant advantages of OFS is its open-source nature. The source code, hardware designs, software code, and technical documents are all open-source and accessible through GitHub. This modularity and accessibility make it easier to build specific solutions for various applications.

Another key benefit of OFS is its timely closed architecture. The architecture consists of the FEM (Front-End Module) and the AFU (Accelerator Function Unit) regions. The FEM provides an integrated I/O ring with common interfaces such as PCIe, Ethernet, memory, debug, and QSFP controller. The AFU region, on the other HAND, offers a standard set of inputs and outputs for building custom workloads, which can be ported across different OFS shell designs, ensuring reusability.

Architecture of OFS for Workload Development

In order to understand how OFS enables workload development, let's take a closer look at its architecture. The OFS architecture consists of the FEM and the AFU regions. The FEM, also known as the shell, provides an integrated I/O ring with common interfaces. It acts as the boundary within which the workload or AFU region lies. The AFU region provides the standard set of inputs and outputs for building specific workloads, which can be easily ported across different OFS-enabled shells or films.

Within the reference design project, Platform Interface Modules (PIMs) act as bridges to convert standard streaming interfaces to memory-mapped or Avalon-based protocols for your workload IP. This modular architecture of OFS makes it flexible, allowing developers to choose between building a static design or a partial reconfiguration (PR) enabled design. A static design is preferred when no updates or swaps in workloads are expected, while a PR-enabled design allows for remote swapping of workloads without reconfiguring the entire FPGA design.

Choosing Between RTO and API Based Design Flow

When using OFS for workload development, developers have the option to choose between an RTO (Reusable Transport Offload) or API (Application Programming Interface) based design flow. The RTO design flow leverages OFS reference designs, tools, and software stack to develop custom workloads or AFUs. This flow is suitable when developers aim for maximum reusability with minimal modification to the existing reference design. On the other hand, the API-based design flow allows developers to have more flexibility and control over the entire development process. It facilitates the development of custom workloads from scratch, leveraging OFS as a starting point.

Building Static or PR Enabled Designs

OFS provides developers with the capability to build both static and PR-enabled designs. A static design, also known as a flat design, is typically used when no updates or swaps in workloads are expected once the system is deployed. This design simplifies the deployment process, as there is no need for frequent reconfiguration. On the other hand, a PR-enabled design enables remote swapping of workloads, allowing developers to update a specific region (AFU) without reconfiguring the entire FPGA design. This flexibility makes PR-enabled designs highly suitable for workloads that require frequent updates or modifications.

Tools and Features of OFS for Workload Development

OFS provides a comprehensive set of tools and features to facilitate workload or AFU development. Automated build scripts are available to simplify the compilation of workloads. Workload examples showcase the features and capabilities of the FEM and software stack. Simulation support tools, such as Synopsis VCS and Simmons Questa simulators, enable developers to simulate and validate their workloads. Additionally, the OFS OPAE (Opaque Program Analysis Environment) software development kit allows for hardware and software co-simulation, making it easier to debug and optimize the performance of workloads. To further aid in debugging, OFS offers the Remote Signal Tap capability, an on-chip debugging tool that captures and displays signals inside the FPGA.

Development Flow for Building an AFU using OFS

Building an AFU or workload using OFS follows a six-step development flow. The first step is to set up your FPGA card or dedicated server with the necessary ingredients, including a compatible operating system, kernel, Cortex Prime Pro software, and OFS repositories. Once set up, you can either build your own AFU or utilize a pre-built film as a starting point for your workload development. This film framework provides standard interfaces and acts as a foundation for your custom AFU.

After building the AFU, it is crucial to test its basic functionality. The AFU simulation environment allows developers to check if the workload runs without errors. In case of any issues, the Remote Signal Tap feature can be used for system testing and analysis. This on-chip debugging tool captures signals inside the FPGA, providing vital insights for troubleshooting and debugging.

Before embarking on your own workload design using OFS, it is recommended to evaluate the framework. OFS provides an out-of-the-box evaluation flow for testing the supplied software and hardware ingredients. Additionally, developers can practice building example AFUs to gain proficiency and prepare for their own custom AFU development.

Evaluating OFS and Testing Software and Hardware

To evaluate OFS, developers can follow an out-of-the-box evaluation flow. This process allows for testing of the provided software and hardware ingredients to understand OFS's capabilities and features. Intel provides a range of acceleration development platforms for testing OFS, including affiliated board vendor cards. Developers can refer to Intel's board catalogs for more information on the available options.

By evaluating OFS and testing its software and hardware components, developers can gain a better understanding of its capabilities, performance, and suitability for their specific workload requirements. This initial evaluation helps in making informed decisions and effectively leveraging OFS for future workload development projects.

Highlights

• OFS (Open FPGA Stack) is a software and hardware infrastructure designed to simplify the development of custom FPGA-based platforms or workloads.
• OFS offers timely optimized reference designs, automated build scripts, and upstream Linux drivers for native OS support.
• The architecture of OFS consists of the FEM (Front-End Module) and the AFU (Accelerator Function Unit) regions, allowing for the portability and reusability of workloads.
• Developers can choose between a static or partial reconfiguration (PR) enabled design based on their specific requirements and the need for workload updates.
• OFS provides a wide range of tools and features for workload development, including automated build scripts, simulation support tools, and the OPAE software development kit.
• The development flow for building an AFU using OFS involves setting up the necessary ingredients, building the AFU, testing its functionality, and evaluating the framework for future workload development.

FAQ

Q: Can OFS be used for developing workloads on FPGA devices other than Agilex?

A: While OFS is primarily designed for Agilex FPGAs, its modular architecture and open-source nature make it suitable for porting workloads to other FPGA devices supported by Intel.

Q: Is OFS suitable for both experienced FPGA developers and beginners?

A: Yes, OFS caters to both experienced developers and beginners. For experienced developers, it provides the flexibility and control needed to develop custom workloads. Beginners can leverage the pre-built reference designs and example AFUs to quickly get started with FPGA development.

Q: Can I contribute to the development of OFS and its associated projects?

A: Yes, OFS is an open-source project, and Intel encourages developers to contribute to its development. The source code and technical documents are accessible through GitHub, making it easy to collaborate and contribute to the community.

Q: Are there any limitations or drawbacks of using OFS for workload development?

A: While OFS offers numerous benefits, it is essential to consider the specific requirements and constraints of your workload. Depending on the complexity and customization needed, certain limitations may arise. It is recommended to thoroughly evaluate OFS and conduct testing to ensure its suitability for your workload development.

Q: Can OFS be integrated with third-party software and APIs for workload development?

A: Yes, OFS supports integration with third-party software and APIs. Its open-source nature and modular design enable developers to incorporate external tools and libraries seamlessly.

Q: Does OFS support virtualization and orchestration of FPGA-based workloads?

A: Yes, OFS includes user-space tools and libraries that facilitate virtualization and orchestration of FPGA-based workloads. This allows for efficient management and deployment of workloads across virtualized environments.

Resources

• Open FPGA Stack (OFS) on GitHub
• Intel Acceleration Development Platforms
• Intel Board Catalog

Note: This is a 100% unique, human-written article with SEO optimization.